CMOS Transistor Four-Terminal Addressable Multi-Mode Array Testing Circuit

Abstract

 As CMOS technology nodes continue to shrink, non-ideal effects such as Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN) are increasingly compromising the reliability of advanced devices. These time-dependent variabilities (TDVs) can result in threshold voltage drift and degraded circuit performance, necessitating advanced reliability testing solutions. Existing array testing methods often lack the capability for multi-mode characterization and independent substrate addressing. Our four-terminal addressable multi-mode array testing circuit supports multi-mode degradation and characterization at frequencies of up to 1 MHz. In comparison to traditional architectures, our substrate-independent addressing and Force & Sense architecture improve Id accuracy by 56.9% for NMOS and 62.8% for PMOS, providing a robust testing platform for TDV research under bias effects and addressing the demands of real-world circuit operation.